2. Since the 1990s, the development of electronic information products has clearly shown two characteristics: first, the complexity of products; second, the time limit for product launch. However, circuit-level design is essentially a single-level design based on gate-level description. All the design work (including design busy, simulation and analysis, design modification, etc.) is performed at the level of basic logic gates. Obviously this A design method cannot adapt to the new situation, and a high-level electronic design method, that is, a system-level design method, emerges as the times require. Previous page Products: Mobile Phone Amplifier Lens, Projector Lens,Fresnel lenses Dongguan Lianlong Photoelectric Technology Co., Ltd , https://www.lianlonggd.com
The high-level design is a "concept-driven" design, and the designer does not need to describe the circuit through the gate-level schematic, but a functional description of the design goal. By getting rid of the limitations of circuit details, designers can focus on the idea of ​​creative solutions and concepts. Once these concepts are entered into the computer in a high-level description, the EDA system can be automated in a rule-driven manner. The entire design. In this way, the new concept can be quickly and effectively become a product, greatly shortening the product development cycle. Not only that, high-level design only defines the behavioral characteristics of the system, and can not involve the realization of the process. Therefore, with the support of the manufacturer's comprehensive library, the comprehensive optimization tool can be used to convert the high-level description into a network table optimized for a certain process. Process conversion has become a breeze.
First, engineers divide the system according to the “top-down†design approach. Second, enter the VHDL code, which is the most common way to lose in high-level design. In addition, you can also use the graphical input method (block diagram, state diagram, etc.), which is intuitive and easy to understand. The third step is to compile the above design into a standard VHDL file. The fourth step is to perform code-level functional simulation, mainly to verify the correctness of the system function design. This step is suitable for large designs, because for large designs, the number of design iterations and time can be greatly reduced by simulating code before synthesis. In general, this simulation step can be omitted. The fifth step is to use the synthesizer to comprehensively optimize the VHDL source code to generate the network table file described by the gate level. This is a key step to convert the high-level description into a hardware circuit. The comprehensive optimization is carried out for a certain product series of ASIC chip suppliers, so the integrated process can be completed with the support of the corresponding manufacturer integrated library. The sixth step is to use the generated network table file to perform timing simulation before adaptation. The simulation process does not involve the hardware characteristics of the specific device, which is relatively rough. For general design, this simulation step can also be omitted. The seventh step is to use the adapter to perform logical mapping operations on the integrated network table file for a specific target device, including the underlying device configuration, logical segmentation, logic optimization, and place and route. The eighth step is to generate a number of design results after the adaptation is completed: (1) the adaptation report, including the internal resource utilization of the chip, the description of the designed Boolean equation, etc.; (2) the adapted simulation model; (3) ) Device programming file. According to the adapted simulation model, the adapted timing simulation can be performed, because the actual hardware characteristics of the device (such as delay characteristics) have been obtained, so the simulation results can accurately predict the actual performance of the future chip. If the simulation results are not up to To the design requirements, you need to modify the VHDL source code or select devices of different speeds and qualities until the design requirements are met. The final step is to load the device programming file generated by the adapter into the target chip FPGA or CPLD through the programmer or download cable. If it is a large-scale product development, it can be easily transferred to the ASIC form by replacing the corresponding factory-tool combination.
In summary, EDA technology is a revolution in the field of electronic design, and is currently in the stage of rapid development, with new EDA tools coming out every year. The majority of electronic engineering personnel master this advanced technology, which is not only the need to improve design efficiency, but also the need for China's electronics industry to survive, compete and develop in the world market.
Development and application of EDA technology (3)